HDL-FSM-Editor for VHDL and Verilog

(See also HDL-SCHEM-Editor for VHDL and Verilog)

HDL-FSM-Editor window showing an example design HDL-FSM-Editor window showing an example design HDL-FSM-Editor window showing an example design

Features:

Advantages:

Prerequisites:

Command-line parameters:

You can use an existent HDL-FSM-Editor project file as command line parameter.


Control-Tab:

Here you define several items which control the generation of the HDL-design, which are:


Interface-Tab:

Here you define the interface of your FSM, this means all inputs, outputs, parameters, libraries.


Internals-Tab:

Here you define the internally used signals of your design.


Diagram-Tab:

Here you draw the graphical representation of your FSM.
The following graphical elements are available:

The following editing actions are available:


Generated HDL-Tab:

Here the generated HDL files are displayed for reading.

  • Each generation replaces the old code with the new code.
  • The generated HDL can be loaded into an editor by "Ctrl-e".
  • When a code line is linked to the graph in the "Diagram-Tab", then the code line will be underlined, when the mouse pointer is at it.
  • To follow the link the user must press the left mouse button together with the Ctrl-key.
  • The diagram element which represents the code line will then be shown and highlighted.

  • Compile Messages Tab:

    The STDOUT and STDERR messages of the compile command appear in this tab.

    Adapting the regular expression for the links:

    HDL-FSM-Editor window showing an example design HDL-FSM-Editor window showing an example design HDL-FSM-Editor window showing an example design HDL-FSM-Editor window showing an example design HDL-FSM-Editor window showing an example design HDL-FSM-Editor window showing an example design

    Here you can find links to 5 designs which I have created.
    All designs are created by HDL-SCHEM-Editor and HDL-FSM-Editor and most of the designs are based at VHDL (only for division also Verilog is available).
    By the link you will find all the needed source-files for both tools and also the generated VHDL/Verilog-files.

    1. Cordic module
    2. multiplication module
    3. Karatsuba multiplication module
    4. division module
    5. division module at signed numbers
    6. SRT division module
    7. square module


    1. The Cordic module "rotate":


    2. The multiplication module "multiply":


    3. The Karatsuba multiplication module "multiply_karatsuba":


    4. The non restoring division module "division":


    5. The non restoring division module "division_signed":


    6. The SRT division module "division_srt_radix2":


    7. The square module "square":

    License:

    HDL-FSM-Editor
    Copyright (c) 2024 Matthias Schweikart

    Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"),
    to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
    and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:

    The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.

    THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
    INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
    IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.

    Files:

    Python3 source code:
    (Start the tool by "python3 hdl_fsm_editor.py" or create an executable with "pyinstaller --onefile hdl_fsm_editor.py")

    Executable for Windows 11:

    Executable for Linux (compiled with Linux-Mint):

    Small example project:

    Change log:

    Version 4.4 (02.10.2024):

    Version 4.3 (30.09.2024):

    Version 4.2 (05.09.2024):

    Version 4.1 (27.08.2024):

    Version 4.0 (14.06.2024):

    Version 3.11 (05.05.2024):

    Version 3.10 (13.03.2024):

    Version 3.9 (07.03.2024):

    Version 3.8 (23.11.2023):

    Version 3.7 (17.11.2023):

    Version 3.6 (08.11.2023):

    Version 3.5 (23.10.2023):

    Version 3.4 (21.10.2023):

    Version 3.3 (18.09.2023):

    Version 3.2 (20.06.2023):

    Version 3.1 (19.06.2023):

    Version 3.0 (30.05.2023):

    Version 2.1 (12.05.2023):

    Version 2.0 (04.05.2023):

    Version 1.9 (09.01.2023):

    Version 1.8 (07.01.2023):

    Version 1.7 (21.12.2022):

    Version 1.6 (09.12.2022):

    Version 1.5 (08.11.2022):

    Version 1.4 (25.10.2022):

    Version 1.3 (10.10.2022):

    Version 1.2 (04.10.2022):

    Version 1.1 (29.09.2022):

    Version 1.0 (25.09.2022):

    If you detect any bugs or have any questions,
    please send a mail to "matthias.schweikart@gmx.de".